A floating gate semiconductor memory device generally includes a plurality of memory cells, each comprising a MOS transistor with a floating gate to store charges. The MOS transistor of the memory cell also includes a control gate, a source region, a drain region, a substrate, and a channel defined as the region between the source region and the drain region. A first insulating layer is formed between the substrate and the floating gate, and a second insulating layer is formed between the floating gate and the control gate. The source and drain regions of the MOS transistor serve as bit lines of the memory cell, while the control gate of the MOS transistor serves as a word line of the memory cell. Each of the control gate, the source, the drain, and the substrate constitutes a terminal of the MOS transistor, and bias voltages may be applied to these terminals. Through different biasing schemes, a bit of information may be written into or erased from the memory cell.
During programming of the memory cell, bias voltages are applied to the terminals of the MOS transistor of the memory cell so that charges in the channel region, such as electrons, gain enough energy to tunnel through the first insulating layer between the substrate and the floating gate. This is generally known “hot-electron tunneling.” For example, the control gate may be biased at a voltage level that is positive with respect to the bias at the source terminal or the drain terminal. As the charges tunnel through the first insulating layer to the floating gate, they are trapped in the floating gate, and, as a result, the threshold voltage of the MOS transistor is changed. Therefore, the threshold voltage can be an indicator of whether the memory cell is in a “0” state or a “1” state.
To erase the information bit from the memory cell, a different bias scheme is applied to the MOS transistor so that a mechanism called Fowler-Nordheim tunneling takes place, and charges stored in the floating gate may “tunnel” out from the floating gate. Fowler-Nordheim tunneling mechanism is well-known to one skilled in the art and will not be described herein. One conventional method of erasing the information bit from a memory cell is to apply a negative bias at the control gate of the MOS transistor and a positive bias at the source terminal, while leaving the drain terminal of the MOS transistor floating. The bias at the negative control gate, together with the bias at the source region, creates an electrical field between the floating gate and the source that forces the electrical charges stored in the floating gate to tunnel to the source region through the first insulating layer. As such, this method is known as “source tunneling.”
However, when these charges tunnel from the floating gate to the source region, there also exists a band-to-band tunneling, i.e., carriers tunneling between two energy bands, over the overlap region between the control gate and source region. This unintended and undesirable band-to-band tunneling becomes more substantial as devices are scaled down in size to adversely effect the operations of the memory device.
Another method of erasing a bit of information stored in the floating ate is to bias the substrate, the source, and the drain of the MOS transistor of the memory cell at a similar voltage level, while biasing the control gate of the memory cell at a voltage level that is negative with respect to the substrate bias. Thus, electron tunneling takes place over the entire channel region of the MOS transistor, and band-to-band tunneling is decreased. This method of erasing is known as “channel erasing,” and is generally considered faster than source erasing.
However, because the erasing operation is performed over a plurality of memory cells at the same time, and these memory cells may not be uniform in size or threshold voltages, the channel erasing method may result in some of the cells being “overly erased,” i.e., the channel region being depleted, and consequently, current leakages between neighboring bit lines, to adversely effect the operations of the memory device.